Photolithography is a fabrication process by which patterns for various devices, such as integrated circuits (IC), are generated on substrate wafers. This process generally starts with the design of an IC chip, including the various circuit elements, their electrical interconnects, and their physical layout across the chip. The IC design typically describes each layer required to fabricate the IC in a FAB using a photolithographic process. There are generally many layers to an IC chip.
After an integrated circuit is designed, a photomask is created. A photomask, or more simply a mask, provides the master image of one layer of a given integrated chip's physical geometries. Masks are critical to the lithography process. There are different types of masks, including binary chrome-on-glass, attenuated phase-shifting masks (attPSM), and alternating phase-shifting masks (altPSM). The mask is usually inspected for defects before being used to replicate the mask image in reduced size onto a wafer by the photolithography system that builds the intended IC. Various mask inspection systems may be used to inspect a mask, including scanning electron microscope (SEM)-based and optical microscope-based systems. Additionally, other non-traditional ‘microscopes’ may be used, including atomic force microscopy (AFM). Furthermore, metrology and other measurement techniques, regardless of dimensionality (1-D, 2-D or 3-D) may also be considered. A mask inspection system compares an image of the mask with another mask or with a mask database to find defects. Defects found in the mask will often be repaired, so that they will not be replicated on or introduce harmful distortions to the chips created from that mask.
A conventional photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer. The photomask is a critical piece of the photolithography process, because it holds the essential integrated circuit design pattern information for the circuits that are replicated from that mask. Masks may be created by various processes. In one method, an electron beam or a laser-based system is used in a photolithographic process to write the pattern on the mask in accordance with mask data developed to produce the intended chip pattern on the wafer.
The resolution limit of today's optical lithography technology is increasingly being challenged by the sub wavelength, or low-k1, dimensions of the critical IC feature geometries. Not only are the critical dimension feature geometries decreasing in size in accordance with, or even faster than, Moore's Law predictions, the already large number of these feature geometries is growing at a dramatic rate as well. Furthermore, due to the necessity to mitigate optical proximity effect distortions through resolution enhancement techniques at the mask level, the overall polygonal figure count is skyrocketing. These critical feature geometries should be patterned and inspected far more precisely as well, due to the severity and sensitivity of the non-linear imaging. (These effects are often referred to in this context as resulting from the mask error enhancement factor, or MEEF). Extreme precision is required for sub wavelength (or low-k1) applications, due to highly non-linear imaging behaviors which often magnify mask errors by large factors.
With the overall year-to-year increase in logic functions performed by an IC, industry trends towards larger and more complex system-on-chip and mixed signal designs, and increasingly aggressive use of artificial Layout Enhancement for Manufacturability (LEM) features such as Resolution Enhancement Technology (RET) and dummy fill patterns, IC physical design layout data volume and resulting mask data file volume sizes are exploding. The overall design and manufacturing process integration complexity is also expanding, as it attempts to span a widening and deepening gap between the different technical disciplines and ‘cultures’ of manufacturing and design. This has led to increases in the length of time to create and inspect masks, in the number of errors impacting mask elements, and in the costs associated with the mask process.
Some of these problems are described with respect to a traditional photolithography process, including mask creation and inspection methods, as shown in FIG. 1. At block 102, an integrated chip (IC) design is created, often by using various EDA systems such as those produced by Cadence Design Systems, Inc., of San Jose, Calif., to effect a desired product design. An IC design flow typically starts with a desired circuit operation, then proceeds to a design layout and a set of circuit elements expected to produce that desired operation. The IC design process 102 usually includes circuit design and analysis, layout synthesis and routing, and verification and tapeout, to produce a set of circuit elements in a layout that can effect a desired circuit's electrical operation on a layer-by-layer basis. This process is often referred to as the design flow. For background on IC design and mask manufacturing processes, see Resolution Enhancement Techniques in Optical Lithography, Chapter 1, by Alfred K. Wong, SPIE Press, 2001, which is incorporated by reference in its entirety.
Up until tapeout, a vast amount of information is available on: the relation of the physical layout to the design schematic or netlist; individual circuit element models and properties; circuit criticalities; and the manufacturing assumptions used in creating the IC design. Furthermore, the information is typically in a design hierarchy of fundamental library base cells, or ‘hard IP,’ in the form of predesigned and characterized blocks or ‘cores.’Circuit elements at this level may include, for example, transistors, power buses, resistors, capacitors, and interconnects. Logos and manufacturing elements, such as area fill cells, may also be included. Tapeout is typically the last process in the IC design flow, and is the ‘handoff’ mechanism to the manufacturing process. Typically, tapeout produces a geometries-only design hierarchical data file in GDS-II stream format. However, a wealth of design knowledge is stripped out of this geometry-only format, and therefore is unavailable to any data file derived from it or any design or manufacturing integration process performed thereafter.
Due to fundamental inherent limitations in current and near-future optical lithography processes, the layout of the IC design is no longer directly equivalent to the pattern printed on the eventual IC wafer. As a result, various Resolution Enhancement Techniques (RETS) may be used to compensate for various distortions, or to enable higher resolution, through advanced optical techniques. For background information on RETs, see Resolution Enhancement Techniques in Optical Lithography. Chapter 1, by Alfred K. Wong, SPIE Press, 2001; and TCAD Development for Lithography Resolution Enhancement, by L. W. Liebmann et al, IBM Journal of Research and Development, Vol. 45, No. 5, September 2001, both of which are incorporated by reference in their entirety. RETs are typically added at the bottom of the design flow, prior to tapeout, and out of view of the designer. However, increasingly more and more RET impact is being dealt with upstream in the design flow, with layout consideration, and even RET insertion, being applied earlier.
A mask data preparation and job deck creation process 104 then follows the creation of the IC design. This starts the mask flow, which runs through mask inspection and repair. Knowledge of the mask writing process, and to some extent the photolithography process, may be employed in “fracturing” the GDS-II design database into a data file for use with the writing tool. Typically, the writing tool uses a MEBES data file format (although other formats may also be used). The MEBES file holds polygon and geometry information to be used in writing the mask. However, like the GDS-II stream file, this file holds none of the higher-level IC design, circuit feature functionality, or criticality information available in the IC design flow. A MEBES file may include information detailing polygonal shapes, dimensions, positions on the mask, manufacturing features added to improve lithographic fidelity at the chip surface, and other parameters. However, there is no ‘knowledge’ of what a feature is beyond its geometry and location. Very little “design” is done at this block, as the IC design process sets the layout and often most of the RET, leaving only fracturing, job deck creation, and secondary chip surface feature additions (such as registration marks) to be handled during the preparation of mask data 104, between IC design 102 and mask writing 106.
A mask writing process 106 follows. Mask writing often involves writing the polygonal shapes and layout of a mask design pattern (often a MEBES file) in a photo- or electron-sensitive coating (often called a “resist”) on a mask substrate (often glass), then etching in chrome, glass or other materials associated with the specific mask technology being employed (such as attPSM or altPSM, for example). Mask writing may be based on various technologies, including electron beam-based or laser-based systems. The fidelity of a mask element written on a mask substrate may be defined by the energy applied, shaped-beam aperture employed, and the adjacency of other features, due to laser, electron or thermo-chemical proximity effects on the mask. Positive effects of increased time and beam energy on element writing may be offset by negative impacts resulting from thermal and chemical changes in the surrounding photoresist caused by the applied energy. There is a tradeoff between optimizing writing speed and the deleterious effects of thermal, chemical and proximity effects related to the writing speed.
A mask writing system is typically provided with and controlled by a database containing polygonal shape and layout information, such as a MEBES data file. At ‘fracturing,’ the mask data is prepared for the mask writing equipment by breaking the complex polygonal shapes into the simple base set of shapes as required and by applying mask writer electron- or laser-spot proximity, shape, exposure compensation, or other sizing operations to the data as needed. Numerous output files may be generated. The design data connectivity and ‘design intent’ have been destroyed by this point. Design data connectivity includes data relating to the electrical net list or schematic, functional intent, and criticality of the various IC elements. Thus, the writing tool, and other downstream activities, such as mask inspection, only receive simple polygonal shapes and location data. There is no knowledge of the design intention of a given polygon, nor any mechanism for establishing a relationship of the polygon to the rest of the design, in order to perform design-aware information processing. In such systems, from that point on, imaging operations of mask writing and inspection operate under the most general uniform imaging assumptions of isotropic imaging. Features are processed under the exact same conditions as their neighbors, and they are spatially invariant and device- and circuit-unaware. Thus, polygonal shapes across the mask are treated equally in terms of their importance to the effectiveness of the resulting circuit. As the IC industry moves to deep sub-wavelength, or ‘low-k1’ layout features, lens aberrations may increasingly violate these space-invariance assumptions, requiring additional higher-level consideration in the design flow as well as the mask flow.
In continuing reference to the example of typical photolithography processes as shown in FIG. 1, after mask writing, a mask inspection process 108 is performed. A mask that has been written or printed with polygonal mask elements is inspected for defects. Examples of mask inspection systems include scanning electron beam, deep UV optical-based, and atomic force microscopy systems. Photomask inspection machines typically include ‘die-to-die’ or ‘die-to-database’ modes of operation, using SEM or optical microscopy illumination. Whereas the die-to-die mode relies upon correlation of features between two die on the same mask plate to allow any differences to be displayed, the die-to-database approach allows correlation against a mask inspection file data. The latter is often preferred, as it offers correlation against ideal data. However, the time demands of the latter can be enormous, resulting in inspection equipment utilizing and requiring increasingly computationally powerful parallel computer architectures. The level of inspection may be determined by the resolution of the inspection system applied to a given mask element or mask area. Defects may include any departures from the mask design, such as missing, misaligned or misshapen pinholes, bridging features, holes, shapes, or a class of ‘cosmetic’ defects which include chrome outside of the working area of the die, contaminates such as glass chips on the edge of the mask, or other anomalies which will not be ‘seen’ by the lithography process nor by the silicon wafer.
Aside from cosmetic defects, defects in a mask are generally assumed to result in defects in an integrated circuit replicated from that mask. The process of classifying and waiving defects on this basis may be performed by a time consuming manual technique. The mask inspection may reference only the polygonal shape and layout information from the mask data file generated by the fracturing tool, often in a file format such as, for example, KLARIS (an abbreviation for KLA-Tencor Reticle Inspection System, produced by KLA-Tencor, Inc. of San Jose, Calif.). Little or no information from the IC design process relating to the function, relative importance, or criticality of individual mask elements is applied in comparing a mask to its mask design template. This is an isotropic approach to mask inspection, where each mask element is inspected equally in terms of the time and resolution of the inspection system, regardless of its relative importance to the operation of the resulting circuit. Additionally, when an unintended artifact is found, there may be no means for interpreting whether this artifact is a defect in the context of its impact on the circuit feature and manufacturing goals.
A defect analysis 110 examines the results of the mask inspection process to discern whether any defects were found. Typically, deviations from the ideal design are considered defects. Some mask defects, however, have no significant negative impact on a circuit produced from the mask, and thus may be ignored as essentially cosmetic, or “non-defects.” Such “non-defects” typically include defects next to mask elements that do not require exact fidelity to effect their function, such as a logo or an area fill cell. Additionally, some defects may have a positive impact, and thus may be ignored or maintained on the mask. Such “positive defects” include, for example, a defect located at a distance (the Rayleigh distance, for example) from a mask element, such that the defect operates as a scattering bar, to enhance the depth of focus of the lithography for that mask element. Such ‘non-defects’ and ‘positive’ defects may be waived or determined not to be defects for purposes of defect analysis and correction.
The defect analysis 110 identifies defects, such as defects near or on the polygonal mask shapes, defects in relative positioning of shapes, or defects of unintended shapes on the mask, such as pinholes, bridging, isolated artifacts or “hard” or “soft” defects. Defects may also include opaque or transparent errors on a mask. Transparent defects may not be visible under certain inspection conditions, or in the alternative may be visible in the inspection condition but not in the use condition. Such transparent defects may impact the phase of light passing through them resulting in unwanted optical interference effects, while opaque defects block or alter such light in some way.
Each found defect is typically examined at defect decision block 112, to determine if it can be repaired or not. Also, the defect decision process 112 determines whether, if unrepairable, the defect can be accepted without repair. This decision may require advanced modeling and simulation of the defect under the specific lithography process conditions being employed. An “unrepairable defect” might, for example, be one that cannot be easily fixed by a repair process, such as focused ion-milling or deposition repair techniques. An unrepairable defect, as determined at decision block 112, causes the mask to be discarded, 116, and a new mask to be written.
If the defect can be repaired, a mask repair process 114 is performed. Mask defect repair often involves focused ion beam (FIB) repair. However, mask repair 114 performed by ion beam milling or other repair processes, may be more time-consuming and expensive than writing a new mask. Additionally, mask repair often creates further defects in a mask, by adding unwanted material during the ion milling process. The repair process may also erode the mask elements in an unwanted manner. Merely handling the mask may alter or damage it through any number of means, including electrostatic discharge (ESD). Therefore, after the mask defect is repaired, a further mask inspection process, 108, is performed, and the results are examined, 110, to determine whether a new defect has been introduced during the repair process. This repetitive cycle of inspecting, repairing, and inspecting again is often costly and time-consuming.
If no defects are found in the mask, or if the defects are waived, then a lithography process for IC chip fabrication 118 is performed. The mask is used in a photolithography system to transfer the mask pattern to a wafer during the integrated chip fabrication process 118. The mask allows light to pass through transparent sections defined by the polygonal mask elements previously written or etched thereon. An image of the mask so produced is then passed through an imaging lens system, often at a reduced image size, and replicated on a wafer surface through a lithography process. Thus, a mask plays a critical role in such systems transmitting the circuit design to the wafer surface.